Call for Papers
Organizers
Program Committee
Program
Past workshops:
HASP 2022
HASP 2021
HASP 2020
HASP 2019
HASP 2018
HASP 2017
HASP 2016
HASP 2015
HASP 2014
HASP 2013
HASP 2012
Although much attention has been directed to the study of security at the system and application levels, security and privacy research focusing on hardware and architecture aspects is still a new frontier. In the era of cloud computing, smart devices, and novel nano-scale devices, practitioners and researchers have to address new challenges and requirements in order to meet the ever-changing landscape of security research and new demands from consumers, enterprises, governments, defense and other industries.
HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications. To that end, papers are solicited from the areas, including, but not limited to:
In addition to regular papers (of at most 8 pages), authors can also submit short papers of at most 5 pages. The titles of the short papers should have "Short Paper:" as their prefix. The program committee may recommend that certain regular papers be accepted and presented at short papers, instead of the regular papers. If authors agree, they will have to shorten their paper and add the prefix to the title prior to publication.
In addition to regular research papers, authors are also invited to submit position
papers or systemization-of-knowledge papers. Position papers should define new problems
in hardware or architecture security and privacy topics. Titles of position papers
should have "Position Paper:" as their prefix.
Systemization-of-Knowledge papers should concisely, but exhaustively, systematize
and conceptualize existing knowledge (similar to SoK papers in S&P conferences,
but focusing on hardware and architecture). Titles of Systemization-of-Knowledge papers
should have "SoK:" as their prefix.
Finally, researchers wishing to share their ongoing work without publishing a paper
should submit application for a Work-in-Progress presentation. To be considered, a short
3-page paper should be submitted, with "WiP:" as the prefix to the title. These papers
will not be published in the proceedings, but the title and authors will be listed on the
HASP web page as a public record of the presentation.
Submission Deadline: Aug. 17, 2023 (extended deadline) by end of day Anywhere on Earth (AoE)
Notification of Acceptance: Sep. 3, 2023
Camera-Ready Version: Sep. 30, 2023
Physical Workshop: Oct. 29, 2023
All submissions must be using the double-column ACM ICPS template. LaTeX template is preferred. Please use the ACM Standard template in the usual two-column format. The template can be found here.
The submissions should be anonymized for double-blind review.
Regular submissions and position papers must be at most 8 pages including the bibliography and appendices (these papers may be recommended for acceptance as short 5 page papers during the review process, but full-length papers should be initially submitted if authors want to be considered for a full-length paper publication). Authors can also directly submit a short paper of at most 5 pages including the bibliography and appendices. Work-in-Progress submissions must be at most 3 pages total (the submission is only for review, Work-in-Progress papers are not published). SoK papers should also be 8 pages, but exceptions can be made, please contact the organizers with any questions.
All accepted regular papers, short papers, position papers, and SoK papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published through ACM ICPS and available through the ACM Digital Library.
Papers can be submitted on the EasyChair web page: https://easychair.org/conferences/?conf=hasp2023.
G. Edward Suh is a Research Scientist at Meta AI. His research interests include computer systems in general with particular focus on computer architecture and security. His current research focuses on building secure computing systems for secure and private machine learning, and using machine learning to improve the security of computer systems. His past work on the AEGIS secure processor is recognized with the test of time award by Intel for its contribution for trusted execution environments deployed across the industry today. He is a Fellow of IEEE.
Jakub Szefer is an Associate Professor of Electrical Engineering at Yale University, where he leads the Computer Architecture and Security Laboratory (CASLAB). His research focuses on computer architecture and hardware security. His research encompasses secure processor architectures, cloud security, FPGA attacks and defenses, hardware FPGA implementation of cryptographic algorithms, and most recently quantum computer cybersecurity. More details about his research can be found at: https://caslab.io/jakub
Gururaj Saileshwar is an Assistant Professor at the University of Toronto. His research is on micro-architectural attacks and defenses with a focus on side-channels and rowhammer attacks. His work typically appears at architecture conferences like ISCA, MICRO, HPCA, ASPLOS and security conferences like IEEE S&P, USENIX Security, and CCS. His work has been recently awarded the IEEE HOST Best PhD Dissertation Award, ACM SIGARCH / IEEE CS TCCA Outstanding Dissertation Award (Honorable Mention), and a IEEE Micro Top Picks (Honorable Mention). His recent work on Rowhammer defenses received the HPCA 2023 Best Paper Award. He received his PhD from Georgia Tech in 2022 and was a Post-Doctoral Researcher at NVIDIA Research in 2023.
Reshma is a security architect at AMD who works on advancing Confidential Computing technologies for the disaggregated, heterogeneous, and distributed data center. In her previous role as a Principal Engineer at Intel’s Security and Privacy Research Lab she led or collaborated in the development of several security innovations for hardening cloud and edge computing. Her breadth of knowledge in platform architecture stems from her earlier work at Intel, developing a range of SW and HW technologies including real time kernel, parallel computing systems, BIOS and FW customization tools and from partnering with academia, industry, and government in advancing the latest hardware technologies. She has several publications and hold 82 patents. Reshma has a Master’s degree in Computer Science from University of Minnesota and Bachelor’s degree in Electrical Engineering from L.D. Engineering College, in India.