Hardware and Architectural Support for Security and Privacy (HASP) 2024

The International Workshop on Hardware and Architectural Support for Security and Privacy (HASP) 2024

Date: November 2, 2024

Location: Austin, Texas, USA -- in conjunction with MICRO 2024

Although much attention has been directed to the study of security at the system and application levels, security and privacy research focusing on hardware and architecture aspects is still a new frontier. In the era of cloud computing, smart devices, and novel nano-scale devices, practitioners and researchers have to address new challenges and requirements in order to meet the ever-changing landscape of security research and new demands from consumers, enterprises, governments, defense and other industries.

HASP is intended to bring together researchers, developers, and practitioners from academia and industry, to share practical implementations and experiences related to all aspects of hardware and architectural support for security and privacy, and to discuss future trends in research and applications. To that end, papers are solicited from the areas, including, but not limited to:

Secure hardware processor architectures and implementations
Side-channel attacks, evaluations, and defenses
Secure cache designs and evaluation, focusing on side-channels
Commercial TEE systems and security solutions
Hardware-enhanced cloud security
Security of emerging architectures, such as Quantum Computers
Hardware support for secure Internet-of-Things
Smartphone hardware security
Hardware fingerprinting and PUFs
Hardware and architectural support for trust management
Hardware trojan threat evaluation, detection, and prevention
Attack resilient hardware and architectural design
Cryptographic hardware design, implementation, and evaluation
Security simulation, testing, validation and verification
Analysis of real attacks and threat evaluation

HASP calls for the following paper types:

Regular Paper (8 Pages, including the bibliography and appendices)
- Research Paper
- SoK: Systemization-of-Knowledge papers should concisely, but exhaustively, systematize and conceptualize existing knowledge (similar to SoK papers in S&P conferences, but focusing on hardware and architecture). Papers should use "SoK Paper:" as their title prefix.
- Position Paper: Position papers should define new problems in hardware or architecture security and privacy topics. Papers should use "Position Paper:" as their title prefix.
Short Paper (4 Pages, including the bibliography and appendices)
- Research Paper: Papers should use "Short Paper:" as their title prefix.
- WiP: Papers should use "WiP:" as their title prefix. Work-in-Progress papers will not appear in the proceedings, but the title and authors will be listed on the HASP web page as a public record of the presentation.

Submission Deadline: Aug. 15, 2024 (extended deadline) by end of day Anywhere on Earth (AoE)

Notification of Acceptance: Sep. 16, 2024

Camera-Ready Version: Sep. 30, 2024

Physical Workshop: Nov. 2, 2024

Papers can be submitted on the EasyChair web page: https://easychair.org/conferences/?conf=hasp2024.

All submissions must be using the double-column ACM ICPS template. LaTeX template is preferred. Please use the ACM Standard template in the usual two-column format. The template can be found here. Regular papers may be up to 8 pages in length, and short papers up to 4 pages, inclusive of bibliography and appendices.

The submissions should be anonymized for double-blind review.

All accepted research papers, SoK papers and position papers will be included in the ACM Digital Library; Work-in-Progress papers are not included. The proceedings will be published through ACM ICPS and available through the ACM Digital Library.

Conflicts of Interest: A paper author has a conflict of interest with a PC member if and only if one or more of the following conditions holds:

The PC member is a co-author of the paper.
The PC member has been a co-worker in the same company or university within the past two years.
The PC member has been a collaborator within the past two years.
The PC member is or was the author’s primary thesis advisor, no matter how long ago.
The author is or was the PC member’s primary thesis advisor, no matter how long ago.
The PC member is a relative or close personal friend of the author.

All paper authors are responsible to reveal any existing conflicts of interest at submission time. Papers with incorrect or incomplete conflict of interest information as of the submission closing time risk rejection

Keynote: Title TBD
Mohit Tiwari (UT Austin)

Mohit Twari is an associate professor and holds the Raytheon Company Faculty Fellowship in the Department of Electrical and Computer Engineering at The University of Texas at Austin. His current research focuses on building secure systems, all the way from hardware to system software to applications that run on them. Tiwari and his team have designed and built the first secure processor that obfuscates all digital signal outputs, including even addresses to physical memory.

Keynote: From Confidential Computing to Zero Trust, Come Along for the (Bumpy?) Ride
Mengmei Ye (IBM)

Mengmei Ye is a Staff Research Scientist working on Confidential Computing and Cloud Infrastructure at IBM T.J. Watson Research Center. She received her Ph.D. degree in Electrical and Computer Engineering from Rutgers University in 2021. Her research work has been recognized with a Distinguished Paper with Artifacts Award at ACSAC 2023, a Best Paper Award at IEEE ICCD 2016, and a Best Paper Nomination at IEEE HOST 2018.

Keynote: Lightening the Shadows: Metadata-Light Exploit Mitigation Based on Novel Cryptography and X86
Michael LeMay (Intel)

Michael LeMay is a Senior Staff Research Scientist in Intel Labs Security and Privacy Research who focuses on memory safety and exploit mitigation. He contributed to several Intel processor security features and open-source exploit mitigation technologies. Michael was Principal Investigator for Intel's Cryptographic Capability Computing (C3) project in the DARPA HARDEN program. He also served as Intel's final lead liaison to the SRC JUMP CONIX research center. Michael received his Ph.D. in Computer Science from the University of Illinois at Urbana-Champaign in 2011 and is a Senior Member of the ACM and IEEE.

Keynote: The Secure Processor Paradox: When Security Metadata Worsens Microarchitecture Security
Fan Yao (University of Central Florida)

Fan Yao is an Assistant professor in the Department of Electrical and Computer Engineering at University of Central Florida. He is leading the Computer Architecture and Systems Research (CASR) lab. His research interests are in the areas of computer architecture, security, machine learning, and energy efficient computing.

HASP 2024 will also organize a mentoring program, which provides student attendees opportunities to get connected with senior researchers individually, and have conversations about their research and career. They will be paired up with faculty/postdoc mentors for meetings during the workshop/conference, and any follow-ups afterward.
Please use this link (https://forms.gle/Fep9a6QwbJ1zW5nh6) to sign up by Oct 14, 2024.